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SUN SBus

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SBus is a computer bus system that was used in most SPARC-based computers from Sun Microsystems during the 1990s



It was introduced in 1989 to be a high-speed bus counterpart to their high-speed SPARC processors, replacing the earlier (and by this time, outdated) VMEbus that had been used in their earlier Motorola 68030-based systems and early SPARC boxes. When Sun was attempting to "open" the SPARC in the early 1990s, SBus was likewise standardized and became IEEE-1496. In 1997 Sun started to migrate away from SBus onto PCI, and today SBus is no longer used.

SBus is in many ways a "clean" design. It was targeted only to the SPARC so many cross-platform issues were simply not a consideration. SBus was based on a big-endian 32-bit address and data bus, run at 25MHz and thus transfers up to 100Mbyte/second. Devices are each mapped onto a 28-bit address space (16 megabytes), and only eight masters are supported although there are an unlimited number of slaves.

When the 64-bit UltraSPARC was introduced SBus was modified to use clock-doubling and transfer two 32-bit data words per cycle to produce a 200MByte/s 64-bit bus. For contrast, modern 66MHz/64-bit PCI is 528MByte/s.

SBus was a peripheral interconnect only (like PCI). Sun systems used another standardized system as a CPU-memory bus, MBus.

Pin Name Description
1GNDGround
2sb_br*sb_br
3sb_sel*sb_sel
4sb_irql*?
5sb_d(0)Data bit 0
6sb_d(2)Data bit 2
7sb_d(4)Data bit 4
8sb_irq2*Interrupt Request 2
9sb_d(6)Data bit 6
10sb_d(8)Data bit 8
11sb_d(10)Data bit 10
12sb_irq3*Interrupt Request 3
13sb_d(12)Data bit 12
14sb_d(14)Data bit 14
15sb_d(16)Data bit 16
16sb_irq4*Interrupt Request 4
17sb_d(19)Data bit 19
18sb_d(21)Data bit 21
19sb_d(23)Data bit 23
20sb_irq5*Interrupt Request 5
21sb_d(25)Data bit 25
22sb_d(27)Data bit 27
23sb_d(29)Data bit 29
24sb_irq6*Interrupt Request 6
25sb_d(31)Data bit 31
26sb_siz(0)sb_siz(0
27sb_siz(2)sb_siz(2
28sb_irq7*Interrupt Request 7
29sb_a(0)Address bit 0
30sb_a(2)Address bit 2
31sb_a(4)Address bit 4
32sb_merr*sb_merr
33sb_a(6)Address bit 6
34sb_a(8)Address bit 8
35sb_a(10)Address bit 10
36sb_err*sb_err
37sb_pa(12)Address bit 12
38sb_pa(14)Address bit 14
39sb_pa(16)Address bit 16
40sb_ack8*sb_ack8
41sb_pa(18)Address bit 18
42sb_pa(20)Address bit 20
43sb_pa(22)Address bit 22
44sb_ack32*sb_ack32
45sb_pa(24)Address bit 24
46sb_pa(26)Address bit 26
47N/CNot connected
48-12V-12 VDC
49sb_clkClock
50sb_bg*sb_bg
51sb_as*sb_as
52GNDGround
53sb_d(1)Data bit 1
54sb_d(3)Data bit 3
55sb_d(5)Data bit 5
56+5V+5 VDC
57sb_d(7)Data bit 7
58sb_d(9)Data bit 9
59sb_d(11)Data bit 11
60GNDGround
61sb_d(13)Data bit 13
62sb_d(15)Data bit 15
63sb_d(17)Data bit 17
64+5V+5 VDC
65sb_d(18)Data bit 18
66sb_d(20)Data bit 20
67sb_d(22)Data bit 22
68GNDGround
69sb_d(24)Data bit 24
70sb_d(26)Data bit 26
71sb_d(28)Data bit 28
72+5V+5 VDC
73sb_d(30)Data bit 30
74sb_siz(1)sb_siz(1
75sb_rdsb_rd
76GNDGround
77sb_a(1)Address bit 1
78sb_a(3)Address bit 3
79sb_a(5)Address bit 5
80+5V+5 VDC
81sb_a(7)Address bit 7
82sb_a(9)Address bit 9
83sb_a(11)Address bit 11
84GNDGround
85sb_pa(13)Address bit 13
86sb_pa(15)Address bit 15
87sb_pa(17)Address bit 17
88+5V+5 VDC
89sb_pa(19)Address bit 19
90sb_pa(21)Address bit 21
91sb_pa(23)Address bit 23
92GNDGround
93sb_pa(25)Address bit 25
94sb_pa(27)Address bit 27
95sb_reset*Reset
96+12V+12 VDC


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