Hardware pinouts information and cables schemes

SO DIMM (144 pin) pinout

memory connector

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Pin Normal ECC Description
1VSSVSSGround
2VSSVSSGround
3DQ0DQ0Data 0
4DQ32DQ32Data 32
5DQ1DQ1Data 1
6DQ33DQ33Data 33
7DQ2DQ2Data 2
8DQ34DQ34Data 34
9DQ3DQ3Data 3
10DQ35DQ35Data 35
11VCCVCC+5 VDC
12VCCVCC+5 VDC
13DQ4DQ4Data 4
14DQ36DQ36Data 36
15DQ5DQ5Data 5
16DQ37DQ37Data 37
17DQ6DQ6Data 6
18DQ38DQ38Data 38
19DQ7DQ7Data 7
20DQ39DQ39Data 39
21VSSVSSGround
22VSSVSSGround
23/CAS0/CAS0Column Address Strobe 0
24/CAS4/CAS4Column Address Strobe 4
25/CAS1/CAS1Column Address Strobe 1
26/CAS5/CAS5Column Address Strobe 5
27VCCVCC+5 VDC
28VCCVCC+5 VDC
29A0A0Address 0
30A3A3Address 3
31A1A1Address 1
32A4A4Address 4
33A2A2Address 2
34A5A5Address 5
35VSSVSSGround
36VSSVSSGround
37DQ8DQ8Data 8
38DQ40DQ40Data 40
39DQ9DQ9Data 9
40DQ41DQ41Data 41
41DQ10DQ10Data 10
42DQ42DQ42Data 42
43DQ11DQ11Data 11
44DQ43DQ43Data 43
45VCCVCC+5 VDC
46VCCVCC+5 VDC
47DQ12DQ12Data 12
48DQ44DQ44Data 44
49DQ13DQ13Data 13
50DQ45DQ45Data 45
51DQ14DQ14Data 14
52DQ46DQ46Data 46
53DQ15DQ15Data 15
54DQ47DQ47Data 47
55VSSVSSGround
56VSSVSSGround
57n/cCB0 
58n/cCB4 
59n/cCB1 
60n/cCB5 
61DUDUDon't use
62DUDUDon't use
63VCCVCC+5 VDC
64VCCVCC+5 VDC
65DUDUDon't use
66DUDUDon't use
67/WE/WERead/Write
68n/cn/cNot connected
69/RAS0/RAS0Row Address Strobe 0
70n/cn/cNot connected
71/RAS1/RAS1Row Address Strobe 1
72n/cn/cNot connected
73/OE/OE 
74n/cn/cNot connected
75VSSVSSGround
76VSSVSSGround
77n/cCB2 
78n/cCB6 
79n/cCB3 
80n/cCB7 
81VCCVCC+5 VDC
82VCCVCC+5 VDC
83DQ16DQ16Data 16
84DQ48DQ48Data 48
85DQ17DQ17Data 17
86DQ49DQ49Data 49
87DQ18DQ18Data 18
88DQ50DQ50Data 50
89DQ19DQ19Data 19
90DQ51DQ51Data 51
91VSSVSSGround
92VSSVSSGround
93DQ20DQ20Data 20
94DQ52DQ52Data 52
95DQ21DQ21Data 21
96DQ53DQ53Data 53
97DQ22DQ22Data 22
98DQ54DQ54Data 54
99DQ23DQ23Data 23
100DQ55DQ55Data 55
101VCCVCC+5 VDC
102VCCVCC+5 VDC
103A6A6Address 6
104A7A7Address 7
105A8A8Address 8
106A11A11Address 11
107VSSVSSGround
108VSSVSSGround
109A9A9Address 9
110A12A12Address 12
111A10A10Address 10
112A13A13Address 13
113VCCVCC+5 VDC
114VCCVCC+5 VDC
115/CAS2/CAS2Column Address Strobe 2
116/CAS6/CAS6Column Address Strobe 6
117/CAS3/CAS3Column Address Strobe 3
118/CAS7/CAS7Column Address Strobe 7
119VSSVSSGround
120/VSS/VSSGround
121DQ24DQ24Data 24
122DQ56DQ56Data 56
123DQ25DQ25Data 25
124DQ57DQ57Data 57
125DQ26DQ26Data 26
126DQ58DQ58Data 58
127DQ27DQ27Data 27
128DQ59DQ59Data 59
129VCCVCC+5 VDC
130VCCVCC+5 VDC
131DQ28DQ28Data 28
132DQ60DQ60Data 60
133DQ29DQ29Data 29
134DQ61DQ61Data 61
135DQ30DQ30Data 30
136DQ62DQ62Data 62
137DQ31DQ31Data 31
138DQ63DQ63Data 63
139VSSVSSGround
140VSSVSSGround
141SDASDA 
142SCLSCL 
143VCCVCC+5 VDC
144VCCVCC+5 VDC


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Pinouts.ru > Memory slots and cards connectors pinouts >  Pinout of SO DIMM (144 pin) and layout of 144 pin SO SIMM connector
Document status: correct
Source(s) of this and additional information: Various productsheets at IBM Memory Products, from Hardware Book, Mark Brown 1 reports
Last updated at Sat Jun 25 2005. Submit additions or corrections for this document. Is this document correct or incorrect? What is your opinion?
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