SO DIMM (72 pin) pinout

memory connector

72 pin SO DIMM connector
at the computer

Pin	Non-Parity	Parity	Description
1	VSS	VSS	Ground
2	DQ0	DQ0	Data 0
3	DQ1	DQ1	Data 1
4	DQ2	DQ2	Data 2
5	DQ3	DQ3	Data 3
6	DQ4	DQ4	Data 4
7	DQ5	DQ5	Data 5
8	DQ6	DQ6	Data 6
9	DQ7	DQ7	Data 7
10	VCC	VCC	+5 VDC
11	PD1	PD1	Presence Detect 1
12	A0	A0	Address 0
13	A1	A1	Address 1
14	A2	A2	Address 2
15	A3	A3	Address 3
16	A4	A4	Address 4
17	A5	A5	Address 5
18	A6	A6	Address 6
19	A10	A10	Address 10
20	n/c	PQ8	Data 8 (Parity 1)
21	DQ9	DQ9	Data 9
22	DQ10	DQ10	Data 10
23	DQ11	DQ11	Data 11
24	DQ12	DQ12	Data 12
25	DQ13	DQ13	Data 13
26	DQ14	DQ14	Data 14
27	DQ15	DQ15	Data 15
28	A7	A7	Address 7
29	A11	A11	Address 11
30	VCC	VCC	+5 VDC
31	A8	A8	Address 8
32	A9	A9	Address 9
33	/RAS3	RAS3	Row Address Strobe 3
34	/RAS2	RAS2	Row Address Strobe 2
35	DQ16	DQ16	Data 16
36	n/c	PQ17	Data 17 (Parity 2)
37	DQ18	DQ18	Data 18
38	DQ19	DQ19	Data 19
39	VSS	VSS	Ground
40	/CAS0	CAS0	Column Address Strobe 0
41	/CAS2	CAS2	Column Address Strobe 2
42	/CAS3	CAS3	Column Address Strobe 3
43	/CAS1	CAS1	Column Address Strobe 1
44	/RAS0	RAS0	Row Address Strobe 0
45	/RAS1	RAS1	Row Address Strobe 1
46	A12	A12	Address 12
47	/WE	WE	Read/Write
48	A13	A13	Address 13
49	DQ20	DQ20	Data 20
50	DQ21	DQ21	Data 21
51	DQ22	DQ22	Data 22
52	DQ23	DQ23	Data 23
53	DQ24	DQ24	Data 24
54	DQ25	DQ25	Data 25
55	n/c	PQ26	Data 26 (Parity 3)
56	DQ27	DQ27	Data 27
57	DQ28	DQ28	Data 28
58	DQ29	DQ29	Data 29
59	DQ31	DQ31	Data 31
60	DQ30	DQ30	Data 30
61	VCC	VCC	+5 VDC
62	DQ32	DQ32	Data 32
63	DQ33	DQ33	Data 33
64	DQ34	DQ34	Data 34
65	n/c	PQ35	Data 35 (Parity 4)
66	PD2	PD2	Presence Detect 2
67	PD3	PD3	Presence Detect 3
68	PD4	PD4	Presence Detect 4
69	PD5	PD5	Presence Detect 1
70	PD6	PD6	Presence Detect 6
71	PD7	PD7	Presence Detect 7
72	VSS	VSS	Ground

This information should be correct, but may be not. Please, help us to improve this document!
Is this document CORRECT or INCORRECT? Your opinion will be used to establish document status (showed at the bottom).

Pinouts.ru > Memory slots and cards connectors pinouts > Pinout of SO DIMM (72 pin) and layout of 72 pin SO DIMM connector	Document status:	correct
Source(s) of this and additional information: Various productsheets at IBM Memory Products, from Hardware Book, Mark Brown, Jim Burd	1 reports
Last updated at Sat Jun 25 2005. Submit additions or corrections for this document.	Is this document correct or incorrect? What is your opinion?

[Discuss at the forum] [Back to index] [SUBMIT new pinout]

This page contain parts under Copyright © 2000-2007 by pinouts.ru team.
No any portion of this webpage may be reproduced in any form without visible direct link to this page provided. Webmaster permission required in any other cases.
Efforts have been made to ensure this page is correct, but it is the responsibility of the user to verify the data is correct for their application.
9006 hits since March 4, 2005